The Empirics of Foreign Reserves

In this paper, we study the determinants of cross-country variation in the level of international reserves over 1981-95. Confirming intuition, trade openness is easily the most important variable. There is also some evidence that financial deepening is associated with an increase in the reserves ratio. Smaller and more volatile industrial countries hold larger reserves than their larger, less volatile counterparts. In addition, more indebted developing countries tend to have smaller reserve ratios. We view these results as establishing some interesting stylized facts that may be helpful in informing future theoretical modelling of reserves behavior.

The Empirics of Foreign Reserves

In this paper, we study the determinants of cross-country variation in the level of international reserves over 1981-95. Confirming intuition, trade openness is easily the most important variable. There is also some evidence that financial deepening is associated with an increase in the reserves ratio. Smaller and more volatile industrial countries hold larger reserves than their larger, less volatile counterparts. In addition, more indebted developing countries tend to have smaller reserve ratios. We view these results as establishing some interesting stylized facts that may be helpful in informing future theoretical modelling of reserves behavior.

ULTRARAM™:Design, Modelling, Fabrication and Testing of Ultra-low-power III-V Memory Devices and Arrays

In this thesis, a novel memory based on III-V compound semiconductors is studied, both theoretically and experimentally, with the aim of developing a technology with superior performance capabilities to established and emerging rival memories. This technology is known as ULTRARAM™. The memory concept is based on quantum resonant tunnelling through InAs/AlSb heterostructures, which are engineered to only allow electron tunnelling at precise energy alignment(s) when a bias is applied. The memory device features a floating gate (FG) as the storage medium, where electrons that tunnel through the InAs/AlSb heterostructure are confined in the FG to define the memory logic (0 or 1). The large conduction band offset of the InAs/AlSb heterojunction (2.1 eV) keeps electrons in the FG indefinitely, constituting a non-volatile logic state. Electrons can be removed from the FG via a similar resonant tunnelling process by reversing the voltage polarity. This concept shares similarities with flash memory, however the resonant tunnelling mechanism provides ultra-low-power, low-voltage, high-endurance and high-speed switching capability. The quantum tunnelling junction is studied in detail using the non-equilibrium Green’s function (NEGF) method. Then, Poisson-Schrödinger simulations are used to design a high-contrast readout procedure for the memory using the unusual type-III band-offset of the InAs/GaSb heterojunction. With the theoretical groundwork for the technology laid out, the memory performance is modelled and a high-density ULTRARAM™ memory architecture is proposed for random-access memory applications. Later, NEGF calculations are used for a detailed study of the process tolerances in the tunnelling region required for ULTRARAM™ large-scale wafer manufacture. Using interfacial misfit array growth techniques, III-V layers (InAs, AlSb and GaSb) for ULTRARAM™ were successfully implemented on both GaAs and Si substrates. Single devices and 2×2 arrays were then fabricated using a top-down processing approach. The memories demonstrated outstanding memory performance on both substrate materials at 10, 20 and 50 µm gate lengths at room temperature. Non-volatile switching was obtained with ≤ 2.5 V pulses, corresponding to a switching energy per unit area that is lower than DRAM and flash by factors of 100 and 1000 respectively. Memory logic was retained for over 24 hours whilst undergoing over 10^6 readout operations. Analysis of the retention data suggests a storage time exceeding 1000 years. Devices showed promising durability results, enduring over 10^7 cycles without degradation, at least two orders of magnitude improvement over flash memory. Switching of the cell’s logic was possible at 500 µs pulse durations for a 20 µm gate length, suggesting a subns switching time if scaled to modern-day feature sizes. The proposed half-voltage architecture is shown to operate in principle, where the memory state is preserved during a disturbance test of > 10^5 half-cycles. With regard to the device physics, these findings point towards ULTRARAM™ as a universal memory candidate. The path towards future commercial viability relies on process development for aggressive device and array-size scaling and implementation on larger Si wafe

Gateway Park Building Design

The purpose of this project is to develop a sustainable design for a mixed-use facility located in the Gateway Park revitalization project of WPI and Worcester, Massachusetts. The proposed design includes both a composite and a reinforced concrete design of structural members, as well as a foundation to transfer the load to the ground. Several elements of green design were incorporated into the building, including geothermal heating and cooling and a living roof. Cost analysis and energy analysis of the building demonstrate the efficiency and sustainability of the proposed building

Simulations of ultra-low power non-volatile cells for random access memory

Dynamic random-access memory (DRAM), which represents 99% of random access memory (RAM), is fast and has excellent endurance, but suffers from disadvantages such as short data retention time (volatility) and loss of data during readout (destructive read). As a consequence, it requires persistent data refreshing, increasing energy consumption, degrading performance and limiting scaling capacity. It is therefore desirable that the next generation of RAM will be non-volatile (NVRAM), low power, high endurance, fast and non-destructively read. Here, we report on a new form of NVRAM: a compound-semiconductor charge-storage memory that exploits quantum phenomena for its operational advantages. Simulations show that the device is extremely low power, with 100 times lower switching energy per unit area than DRAM, but with similar operating speeds. Non-volatility is achieved due to the extraordinary band offsets of InAs and AlSb, providing a large energy barrier (2.1 eV) which prevents the escape of electrons. Based on the simulation results, an NVRAM architecture is proposed for which extremely low disturb-rates are predicted as a result of the quantum-mechanical resonant-tunnelling mechanism used to write and erase

Induced CNS expression of CXCL1 augments neurologic disease in a murine model of multiple sclerosis via enhanced neutrophil recruitment.

Increasing evidence points to an important role for neutrophils in participating in the pathogenesis of the human demyelinating disease MS and the animal model EAE. Therefore, a better understanding of the signals controlling migration of neutrophils as well as evaluating the role of these cells in demyelination is important to define cellular components that contribute to disease in MS patients. In this study, we examined the functional role of the chemokine CXCL1 in contributing to neuroinflammation and demyelination in EAE. Using transgenic mice in which expression of CXCL1 is under the control of a tetracycline-inducible promoter active within glial fibrillary acidic protein-positive cells, we have shown that sustained CXCL1 expression within the CNS increased the severity of clinical and histologic disease that was independent of an increase in the frequency of encephalitogenic Th1 and Th17 cells. Rather, disease was associated with enhanced recruitment of CD11b+ Ly6G+ neutrophils into the spinal cord. Targeting neutrophils resulted in a reduction in demyelination arguing for a role for these cells in myelin damage. Collectively, these findings emphasize that CXCL1-mediated attraction of neutrophils into the CNS augments demyelination suggesting that this signaling pathway may offer new targets for therapeutic intervention

Disrupted CXCR2 Signaling in Oligodendroglia Lineage Cells Enhances Myelin Repair in a Viral Model of Multiple Sclerosis.

CXCR2 is a chemokine receptor expressed on oligodendroglia that has been implicated in the pathogenesis of neuroinflammatory demyelinating diseases as well as enhancement of the migration, proliferation, and myelin production by oligodendroglia. Using an inducible proteolipid protein (Plp) promoter-driven Cre-loxP recombination system, we were able to assess how timed ablation of Cxcr2 in oligodendroglia affected disease following intracranial infection with the neurotropic JHM strain of mouse hepatitis virus (JHMV). Generation of Plp-Cre-ER(T)::Cxcr2flox/flox transgenic mice (termed Cxcr2-CKO mice) allows for Cxcr2 to be silenced in oligodendrocytes in adult mice following treatment with tamoxifen. Ablation of oligodendroglia Cxcr2 did not influence clinical severity in response to intracranial infection with JHMV. Infiltration of activated T cells or myeloid cells into the central nervous system (CNS) was not affected, nor was the ability to control viral infection. In addition, the severity of demyelination was similar between tamoxifen-treated mice and vehicle-treated controls. Notably, deletion of Cxcr2 resulted in increased remyelination, as assessed by g-ratio (the ratio of the inner axonal diameter to the total outer fiber diameter) calculation, compared to that in vehicle-treated control mice. Collectively, our findings argue that CXCR2 signaling in oligodendroglia is dispensable with regard to contributing to neuroinflammation, but its deletion enhances remyelination in a preclinical model of the human demyelinating disease multiple sclerosis (MS).IMPORTANCE Signaling through the chemokine receptor CXCR2 in oligodendroglia is important for developmental myelination in rodents, while chemical inhibition or nonspecific genetic deletion of CXCR2 appears to augment myelin repair in animal models of the human demyelinating disease multiple sclerosis (MS). To better understand the biology of CXCR2 signaling on oligodendroglia, we generated transgenic mice in which Cxcr2 is selectively ablated in oligodendroglia upon treatment with tamoxifen. Using a viral model of neuroinflammation and demyelination, we demonstrate that genetic silencing of CXCR2 on oligodendroglia did not affect clinical disease, neuroinflammation, or demyelination, yet there was increased remyelination. These findings support and extend previous findings suggesting that targeting CXCR2 may offer a therapeutic avenue for enhancing remyelination in patients with demyelinating diseases

Demonstration of a Fast, Low-Voltage, III-V Semiconductor, Non-Volatile Memory

ULTRARAM™ is a III-V semiconductor memory technology which exploits resonant tunneling to allow ultra-low-energy memory logic switching (per unit area), whilst retaining non-volatility. Single-cell memories developed on GaAs substrates with a revised design and atomic-layer-deposition Al 2 O 3 gate dielectric demonstrate significant improvements compared to prior prototypes. Floating-gate (FG) memories with 20-μm gate length show 0/1 state contrast from 2.5-V program-read-erase-read (P/E) cycles with 500-μs pulse duration, which would scale to sub-ns switching speed at 20-nm node. Nonvolatility is confirmed by memory retention tests of 4×10 3 s with both 0 and 1 states completely invariant. Single cells demonstrate promising endurance results, undergoing 10 4 cycles without degradation. P/E cycling and disturbance tests are performed using half-voltages (±1.25 V), validating the high-density random access memory (RAM) architecture proposed previously. Finally, memory logic is retained after an equivalent of >10 5 P/E disturbances

ULTRARAM:toward the development of a III-V semiconductor, non-volatile, random-access memory

ULTRARAM™ is a III-V compound semiconductor memory concept which exploits quantum resonant tunneling to achieve non-volatility at extremely low switching energy per unit area. Prototype devices are fabricated in a 2x2 memory array formation on GaAs substrates. The devices show 0/1 state contrast from program/erase (P/E) cycles with 2.5 V pulses of 500-µs duration, a remarkable switching speed for a 20 µm gate length. Memory retention is tested for 8x104 s, whereby the 0/1 states show adequate contrast throughout, whilst performing 8x104 readout operations. Further reliability is demonstrated via program-read-erase-read endurance cycling for 106 cycles with 0/1 contrast. A half-voltage array architecture proposed in our previous work is experimentally realized, with an outstandingly small disturb rate over 105 half-voltage cycles